1. Field of the Invention
The present invention relates to chip testing circuits, and more specifically to a flexible on-chip testing circuit for I/Os characterization of different types of I/O structures.
2. Discussion of the Related Art
Input/Output (I/O) buffers are features of an integrated circuit which must be thoroughly tested because it is the I/O element which finally interfaces the core signal to the off-chip environment. The test of I/O circuitry involves measurement of various I/O pin DC and AC parameters. Since fabrication complexities have increased, hence tests have to be targeted not only to debug design related issues but also process related ones as considerable process spread is observed in newer technologies. This makes it mandatory for any design to be qualified on a large number of dies and wafers with emphasis on corner lot characterization. Such characterization test would require a sophisticated expensive tester and also increase test duration if the tests are performed manually. Embedded test features for macros such as memories have already proved to be an effective solution to expensive testers and parametric analyzers. Although commercial on-chip test solutions exist for other macros, most of the tests done today for the measurement of I/O pin parameters starting from the application of test patterns to the observation and compilation of results are manual thus making the tests, time intensive and prone to instrument errors. Moreover characterization tests are performed on a few packaged dies, which do not guarantee design robustness with process spread. Moreover not all features (such as maximum operating frequency of an input (IUT) can be measured at tester level.
Wafer-level tests, with their automated test programs offer an optimal solution in reducing the test time. Another key aspect is the time involved for debugging, when silicon results do not adhere to the specifications. This would require a very sophisticated tester thus enormously adding to the cost of test. On-chip I/O test and characterization structures, which facilitate board-level as well as wafer-level testing on a low-cost tester with minimum test duration address all the above mentioned challenges.
There are various parameters, which need to be analyzed for understanding special characteristics of the I/O structures. The parameters can be broadly classified as the DC parameters include output voltages and currents, the input voltage threshold levels and the pin leakage currents, whereas the Transient parameters include propagation delay, voltage rise/fall times of output I/Os (as they drive large off chip capacitances) and maximum frequency of operation of the I/O circuits in input as well as output modes. The frequency measurements can be of immense help to the core designer, as he/she exactly knows the limiting frequencies of I/Os for applying critical signals like clock and observing the output values. The above parameters often become extremely significant in a VLSI designing, like DRAM circuits, analog to digital converter (ADC) circuits, etc.
Therefore, there is need for a novel on-chip testing mechanism, which can provide a flexible on-chip characterization solution for different types of I/O structures. The novel mechanism employs an op-code based programmable test program and algorithms with a simple and standard Test Program/Tester Setup with automatic processing of tester results thereby resulting in an appreciable reduction in the test time. The mechanism is a cost effective approach for testing, and provides sufficient flexibility to measure D/C as well as A/C characteristics.